In some analog chip applications, an integrated circuit die may be co-packaged with a discrete device die having Metal Oxide Semiconductor Field Effect Transistors (MOSFET), Junction Field Effect Transistors (JFET), and/or suitable other devices. In some applications, the contact pads of both the integrated circuit die and the discrete device die are on the same side. Lateral devices such as Lateral Double Diffused MOSFET (LDMOS) can easily meet this requirement. However, in many other applications, it may be difficult. For example, discrete devices typically have a requirement on low-on resistance (RON) and a small area. Thus, the parameter RON*AREA is important. Discrete devices such as vertical MOSFET, vertical JFET or Field Effect Transistor (FET) with integrated Schottky diodes can achieve lower cost and much lower RON than LDMOS partly because the drain or the cathode includes the entire back surface of the die. Thus, some applications for such co-packaged products require that the backside drain/cathode of the vertical discrete die contacts the topside surface of the die by a via.
FIG. 1A is a cross-sectional view of a conventional vertical MOSFET 100 as one example in accordance with the prior art. The MOSFET device 100 comprises a highly doped N+ substrate 10 at the bottom side as the drain. At the topside, gate regions 12, P type body regions 13 and N type source regions 11 are fabricated in the N− epitaxial layer 15. In the embodiment shown in FIG. 1A, the gate regions 12 are formed by trenches in the N− epitaxial layer 15 filled with polysilicon. Around the sidewalls of the trenched gate regions 12, gate oxide 120 is aligned to separate the gate regions 12 from the P type body regions 13 and the N− epitaxial layer 15. The N+ source regions 11 are formed in the body regions 13 from the topside surface and are adjacent to the gate oxide 120 of the gate regions 12.
The source regions 11 are connected together by electrically conducting interconnection 111 and are connected electrically to source contact pad/pads 1110 to form the source electrode S. The gate regions 12 are connected together by electrically conducting interconnection (not shown in this section) and are connected electrically to the gate contact pad/pads to form the gate electrode G. A metal layer contacted to the entire back side of the substrate 10 functions as the drain electrode D. In one embodiment, the electrically conducting interconnections and the contact pads are made of metal such as copper. The source regions 11 and the body regions 13 are shorted. As shown in FIG. 1A, trench/trenches 112 are among the N+ source regions 11 and reach into the P body regions 13, then metal is deposited in the trenches 112 to form the contacts and source interconnections 111. The body regions 13 and the source regions 11 are electrically shorted and led out to the source contact pads 1110 by the source interconnections 111.
In other conventional devices, the source regions 11 and the body regions 13 are shorted through an extended source contact as shown in FIG. 1B. In this approach, the source interconnections 111B have an extended contact area and electrically contact both the source region 11 and the body region 13. P+ body contact regions 131 above the P body regions 13 and the source regions 11 are formed optionally to short the source regions 11 and the body regions 13, as shown in FIG. 1C. However, the cell area will be larger than the embodiment in FIG. 1A due to the large contact required for a P+ body contact region.
FIG. 2 shows a topside view of a conventional discrete vertical device 200 in accordance with the prior art. From the topside surface, source plate 21 and gate plate 22 are laid out. The source plate 21 contacts the topside source regions of a vertical device through interconnection. In one embodiment the source plate forms part of the interconnection structure. The gate plate 22 contacts the topside gate regions of the vertical device through interconnection. On the source plate 21, source contact pads 211 are formed. Also, gate contact pad/pads 221 are formed on the gate plate 22.
As such, the gate and the source of the vertical device are electrically isolated by separated gate plate and source plate. The drain/cathode of the vertical device is on the backside substrate of the discrete device die 200 and the drain plate is laid out at the bottom surface of the discrete device die 200. In a typical device, the whole bottom surface is covered with a metal as the drain.